Atin Sood, Benjamin Elder, et al.
arXiv
The utilization of timing closure based integrated technology in the manufacturing of deep-submicron integrated circuit (IC) designs is discussed. As interconnect delay dominates the overall chip performance, achieving of accurate timing optimization and delay prediction is inherent for improving circuit performance. IBM's Place-Driven Synthesis (PDS) system describes an effective flow for achieving technology closure. The prerequisites for the PDS system and timing-driven placement and logic optimization, which include buffering and resizing optimization, are discussed.
Atin Sood, Benjamin Elder, et al.
arXiv
Kerry Bernstein, Paul Andry, et al.
DAC 2007
Hua Xiang, Liang Deng, et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Luyao Shi, Michael Kazda, et al.
LAD 2024