L.G. Heller, L.M. Terman
IEEE JSSC
The design and performance characteristics of a 128X64 MOS transistor memory is given. The storage cell used operates with a low standby power, 0.1 mW. The memory operates with a 12-ns access time, 35-ns read cycle time, and a 60-ns write cycle time. Copyright © 1966 by The Institute of Electrical and Electronics Engineers, Inc.
L.G. Heller, L.M. Terman
IEEE JSSC
L.M. Terman
ICSICT 1995
L.M. Terman
ISSCC 1978
A. Deutsch, H. Smith, et al.
IEEE Topical Meeting EPEPS 1997