Thomas E. Karis, C. Mark Seymour, et al.
Rheologica Acta
Impact of device structure variability of silicon nanowire FETs is assessed and SRAM design implication is presented based on 3-D numerical simulation. Both the conventional and junctionless nanowire FETs are shown to be sensitive to structural variation whereas the former is more tolerable. Both the circular wire and non-circular wire cases for feasible SRAM design with a focus on read/write noise margin are included in our study. © 2011 Elsevier Ltd. All rights reserved.
Thomas E. Karis, C. Mark Seymour, et al.
Rheologica Acta
U. Wieser, U. Kunze, et al.
Physica E: Low-Dimensional Systems and Nanostructures
J.H. Stathis, R. Bolam, et al.
INFOS 2005
P. Alnot, D.J. Auerbach, et al.
Surface Science