Conference paper
Redesign using state splitting
Raul Camposano, Reinaldo A. Bergamaschi
EDAC 1990
Automating the design of system on a chip (SOC) using cores technique was presented. The cores or intellectual property (IP) blocks are used to quickly create SOC design with required complexity. The coreConnect architecture provides three buses namely processor local bus (PLB), on-chip peripheral bus (OPB) and device control-register (DCR) interconnects for interconnecting cores and custom logics. This technology brings a high-level abstraction to SOC design which enables easy reuse of existing components.
Raul Camposano, Reinaldo A. Bergamaschi
EDAC 1990
Reinaldo A. Bergamaschi, Youngsoo Shin, et al.
CODES+ISSS 2003
Reinaldo A. Bergamaschi
SLIP 2004
Subhrajit Bhattacharya, John Darringer, et al.
ISQED 2005