Representative traces for processor models with infinite cache
V.S. Iyengar, Louise Trevillyan, et al.
HPCA 1996
This paper describes a system (AVPGEN) for generating tests (called architecture verification programs or AVP’s) to check the conformance of processor designs to the specified architecture. To generate effective tests, AVPGEN uses novel concepts like symbolic execution and constraint solving, along with various biasing techniques. Unlike many earlier systems that make biased random choices, AVPGEN often chooses intermediate or final values and then solves for initial values that can lead to the desired values. A language called SIGL (symbolic instruction graph la nguage) is provided in AVPGEN for the user to specify templates with symbolic constraints. The combination of user-specified constraints and the biasing functions is used to focus the tests on conditions that are interesting in that they are likely to activate various kinds of bugs. The system has been used successfully to debug many S/390 processors and is an integral part of the design process for these processors. © 1995 IEEE
V.S. Iyengar, Louise Trevillyan, et al.
HPCA 1996
A.K. Chandra, V.S. Iyengar, et al.
ICCD 1994
Sandip Kundu, I. Nair, et al.
European Conference on Design Automation 1992
Z. Barzilai, V.S. Iyengar, et al.
IEEE ITC 1984