An SRAM-Based Multibit In-Memory Matrix-Vector Multiplier with a Precision That Scales Linearly in Area, Time, and Power
- Riduan Khaddam-Aljameh
- Pier Andrea Francese
- et al.
- 2021
- IEEE Transactions on VLSI Systems
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A 4-Transistors/1-Resistor Hybrid Synapse Based on Resistive Switching Memory (RRAM) Capable of Spike-Rate-Dependent Plasticity (SRDP)
- Valerio Milo
- Giacomo Pedretti
- et al.
- 2018
- IEEE Transactions on VLSI Systems
A Heterogeneous and Programmable Compute-In-Memory Accelerator Architecture for Analog-AI Using Dense 2-D Mesh
- Shubham Jain
- Hsinyu Tsai
- et al.
- 2023
- IEEE Transactions on VLSI Systems
Power Delivery Design, Signal Routing, and Performance of On-Chip Cobalt Interconnects in Advanced Technology Nodes
- Nicholas A. Lanzillo
- Albert Chu
- et al.
- 2021
- IEEE Transactions on VLSI Systems
Architecture optimization and performance comparison of nonce-misuse-resistant authenticated encryption algorithms
- Sandhya Koteshwara
- Amitabh Das
- et al.
- 2019
- IEEE Transactions on VLSI Systems
Sparse regression driven mixture importance sampling for memory design
- Maria Malik
- Rajiv V. Joshi
- et al.
- 2018
- IEEE Transactions on VLSI Systems
Excavating the hidden parallelism inside DRAM architectures with buffered compares
- Jinho Lee
- Jongwook Chung
- et al.
- 2017
- IEEE Transactions on VLSI Systems
Energy-Efficient Adaptive Hardware Accelerator for Text Mining Application Kernels
- Robert Karam
- Ruchir Puri
- et al.
- 2016
- IEEE Transactions on VLSI Systems
Embedding read-only memory in spin-transfer torque MRAM-based on-chip caches
- Xuanyao Fong
- Rangharajan Venkatesan
- et al.
- 2016
- IEEE Transactions on VLSI Systems
A universal hardware-driven PVT and layout-aware predictive failure analytics for SRAM
- Rajiv V. Joshi
- Sudesh Saroop
- et al.
- 2016
- IEEE Transactions on VLSI Systems