Charge trapping in high K gate dielectric stacks
Sufi Zafar, Alessandro Callegari, et al.
IEDM 2002
Using a Monte Carlo method, we investigate hole transport in ultrasmall p-channel Si MOSFETs with gate lengths of 25 nm. The device simulator couples a 2D Poisson solver with a discretized 6 × 6 k.p Hamiltonian solver that includes the effect of the confining potential and provides the subband structure in the channel region. In addition, carriers in the source and drain regions are treated as quasi 3D particles and the band-structure information is included by solving for the eigenenergies of a more compact 6 × 6 k.p Hamiltonian. © 2005 Springer Science + Business Media, Inc.
Sufi Zafar, Alessandro Callegari, et al.
IEDM 2002
Massimo V. Fischetti, D.J. Dimaria
Physical Review Letters
Wilfried Haensch, Edward J. Nowak, et al.
IBM J. Res. Dev
Arvind Kumar, Massimo V. Fischetti, et al.
SISPAD 2005