Clock tree and power grid design > 1 GHz

This paper illuminates the effects of on-chip inductance through the discussion of several illustrative on-chip wiring examples analyzed using fullwave extraction and simulation methods. Effects such as overshoot, reflections, frequency dependent effective resistance and inductance are illustrated using animated visualizations of the full-wave simulations. Simple examples of design techniques to avoid, mitigate, and even take advantage of on-chip inductance effects will be described, and successful tuning of large GHz-class chip interconnect networks for exceptionally low global clock skew is demonstrated.