Dealing with inductance in high-speed chip design
- P. Restle
- A.E. Ruehli
- et al.
- 1999
- DAC 1999
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10 results for Steven G. Walker
First-order incremental block-based statistical timing analysis
- Chandramouli Visweswariah
- K. Ravindran
- et al.
- 2004
- DAC 2004
Clock tree and power grid design > 1 GHz
- Phillip J. Restle
- Albert Ruehli
- et al.
- 2000
- ADMETA 2000
CPAM: A common power analysis methodology for high-performance VLSI design
- J.Scott Neely
- Howard H. Chen
- et al.
- 2000
- IEEE Topical Meeting EPEPS 2000
Design, fabrication, and automated testing of 32-channel integrated MSM/MESFET optoelectronic integrated circuit (OEIC) receiver arrays
- D.L. Rogers
- S. Walker
- et al.
- 1995
- SPIE Photonics West 1995
Design, fabrication, and automated testing of 32 channel integrated MSM/MESFET OEIC receiver arrays
- D.L. Rogers
- S. Walker
- et al.
- 1994
- IEE/LEOS Summer Topical Meetings 1994
An integrated CAD methodology for evaluating MOSFET and parasitic extraction models and variability
- K. Koushik Das
- Steven G. Walker
- et al.
- 2007
- Proceedings of the IEEE
First-order incremental block-based statistical timing analysis
- Chandu Visweswariah
- Kaushik Ravindran
- et al.
- 2006
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Full-wave PEEC time-domain method for the modeling of on-chip interconnects
- Phillip J. Restle
- Albert E. Ruehli
- et al.
- 2001
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Technology Development of a High-Density 32-Channel 16-Gb/s Optical Data Link For Optical Interconnection Applications for the Optoelectronic Technology Consortium (OETC)
- Yiu-Man Wong
- Dirk J. Muehlner
- et al.
- 1995
- Journal of Lightwave Technology