Kevin J. Nowka, Gary D. Carpenter, et al.
IEEE Journal of Solid-State Circuits
Limited switch dynamic logic (LSDL), a high performance logic circuit, has been modified by introducing a pseudo-nMOS style load. The resultant circuit consumes less power, primarily due to the reduction of capacitance on the clock network. The controlled-load LSDL is shown to be more robust to noise and power rail bounce. A 64-bit rotator circuit was used in the analysis. The effect of process variation on circuit performance is also evaluated. © 2005 IEEE.
Kevin J. Nowka, Gary D. Carpenter, et al.
IEEE Journal of Solid-State Circuits
Sani R. Nassif, Zhuo Li
ISQED 2005
Peter J. Klim, John Barth, et al.
IEEE Journal of Solid-State Circuits
Alan J. Drake, Kevin J. Nowka, et al.
IEEE Journal of Solid-State Circuits