Conference paper
Cache restoration for highly partitioned virtualized systems
David Daly, Harold W. Cain
HPCA 2012
To alleviate bottlenecks in this era of many-core architectures, the authors propose a virtual write queue to expand the memory controller's scheduling window through visibility of cache behavior. Awareness of the physical main memory layout and a focus on writes can shorten both read and write average latency, reduce memory power consumption, and improve overall system performance. © 2011 IEEE.
David Daly, Harold W. Cain
HPCA 2012
Marcio Silva, Mohammad Banikazemi, et al.
IBM J. Res. Dev
David Daly, Dong Ryu Kyung, et al.
WHPCF 2008
David Daly, Marcio A. Silva, et al.
IPDPS 2008