James R. Schwank, Marty R. Shaneyfelt, et al.
IEEE TNS
This paper presents modeling and measurements of single event transients in a commercial 45 nm SOI device technology. SETs in clock circuits and pass gates can cause upsets in circuit structures hardened against single event upsets. © 2006 IEEE.
James R. Schwank, Marty R. Shaneyfelt, et al.
IEEE TNS
Martha V. O'Bryan, Kenneth A. LaBel, et al.
REDW/NSREC 2011
James R. Schwank, Marty R. Shaneyfelt, et al.
IEEE TNS
James R. Schwank, Marty R. Shaneyfelt, et al.
RADECS 2011