Conference paper
Multi-bit upsets in 65nm SOI SRAMs
Ethan H. Cannon, Michael S. Gordon, et al.
IRPS 2008
Paper
Design implications of single event transients in a commercial 45 nm SOI device technology
Abstract
This paper presents modeling and measurements of single event transients in a commercial 45 nm SOI device technology. SETs in clock circuits and pass gates can cause upsets in circuit structures hardened against single event upsets. © 2006 IEEE.
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