Design methodology for a large communication chip

Rolf Clauberg; Peter Buchmann; Andreas Herkersdorf; David J. Webb

doi:10.1109/54.867899

IEEE Design and Test of Computers

Paper

01 Jul 2000

Design methodology for a large communication chip

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Abstract

Smart chip is a large communication chip with standard-based communication interfaces, multiple clock domains, and mixed-signal components for line interfacing. This chip has been developed by focusing mainly on general design aspects.

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Abstract

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A low-power 40 Gbit/s receiver circuit based on full-swing CMOS-style clocking

A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology

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