Some experimental results on placement techniques
Maurice Hanan, Peter K. Wolff, et al.
DAC 1976
The IBM POWER7® microprocessor, which is the next-generation IBM POWER® processor, leverages IBM's 45-nm silicon-on-insulator (SOI) process with embedded dynamic random access memory to achieve industry-leading performance. To deliver this complex 567-mm2 die, the IBM design team made significant innovations in chip design methodology. This paper describes the most critical methodology innovations specific to POWER7 design, which were in modularity, timing closure, and design efficiency. © 2011 by International Business Machines Corporation.
Maurice Hanan, Peter K. Wolff, et al.
DAC 1976
Zohar Feldman, Avishai Mandelbaum
WSC 2010
Xinyi Su, Guangyu He, et al.
Dianli Xitong Zidonghua/Automation of Electric Power Systems
Marshall W. Bern, Howard J. Karloff, et al.
Theoretical Computer Science