'Timing Closure by Design,' a high frequency microprocessor design methodology
- S.D. Posluszny
- Naoaki Aoki
- et al.
- 2000
- DAC 2000
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10 results for S.D. Posluszny
A 1GHz single-issue 64b powerPC processor
- H.P. Hofstee
- Naoaki Aoki
- et al.
- 2000
- ISSCC 2000
Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor
- Dac Pham
- Hans-Werner Anderson
- et al.
- 2006
- ASP-DAC 2006
The design methodology and implementation of a first-generation CELL processor: A multi-core SoC
- D.C. Pham
- E. Behnen
- et al.
- 2005
- CICC 2005
Design methodology for a 1.0 GHz microprocessor
- S.D. Posluszny
- Naoaki Aoki
- et al.
- 1998
- ICCD 1998
IBM POWER8 circuit design and energy optimization
- Victor Zyuban
- Joshua Friedrich
- et al.
- 2015
- IBM J. Res. Dev
Design methodology for the IBM POWER7 microprocessor
- Joshua Friedrich
- Ruchir Puri
- et al.
- 2011
- IBM J. Res. Dev
Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor
- D.C. Pham
- T. Aipperspach
- et al.
- 2006
- IEEE Journal of Solid-State Circuits
1.0-GHz single-issue 64-bit PowerPC integer processor
- Joel Silberman
- Naoaki Aoki
- et al.
- 1998
- IEEE Journal of Solid-State Circuits
Designing for a gigahertz
- H. Peter Hofstee
- Sang H. Dhong
- et al.
- 1998
- IEEE Micro