Sophie Verdonckt-Vandebroek, Bernard S. Meyerson, et al.
IEEE Transactions on Electron Devices
Digital droop sensors (DDSs) with core throttling mitigate microprocessor voltage droops and enable a voltage control loop (undervolting) to offset loadline uplift plus noise effects, protecting reliability . These combine with a runtime algorithm for workload optimized frequency (WOF) that deterministically maximizes core frequency. The combined effect is demonstrated across a range of workloads, including SPEC, and provides up to a 15% frequency boost and a 10% reduction in core voltage.
Sophie Verdonckt-Vandebroek, Bernard S. Meyerson, et al.
IEEE Transactions on Electron Devices
Phillip J. Restle, Craig A. Carter, et al.
Digest of Technical Papers-IEEE International Solid-State Circuits Conference
Nikolaos Chrysos, Fredy Neeser, et al.
Computer Networks
Terry I. Chappell, Stanley E. Schuster, et al.
IEEE Journal of Solid-State Circuits