Steven C. Chan, Kenneth L. Shepard, et al.
IEEE Journal of Solid-State Circuits
Digital droop sensors (DDSs) with core throttling mitigate microprocessor voltage droops and enable a voltage control loop (undervolting) to offset loadline uplift plus noise effects, protecting reliability . These combine with a runtime algorithm for workload optimized frequency (WOF) that deterministically maximizes core frequency. The combined effect is demonstrated across a range of workloads, including SPEC, and provides up to a 15% frequency boost and a 10% reduction in core voltage.
Steven C. Chan, Kenneth L. Shepard, et al.
IEEE Journal of Solid-State Circuits
Yuan Taur, D.S. Zicherman, et al.
IEEE Electron Device Letters
Matthew M. Ziegler, Ruchir Puri, et al.
CICC 2014
Liang-Teck Pang, Phillip J. Restle, et al.
VLSI Circuits 2012