Effects of gate-to-body tunneling current on PD/SOI CMOS SRAM

Abstract

The effects of gate tunneling current on high performance, static random access memory (SRAM) designed in bulk complementary metal oxide semiconductor (CMOS) technology were described. The SRAMs, fabricated by using partially depleted silicon on insulator (PD-SOI) technology, achieved 2.0 GHz cycle time and 430 picosecond access time. The memory utilized pseudo-static circuits for robust timing and to facilitate migration to PD/SOI technology.