Stress proximity technique for performance improvement with dual stress liner at 45nm technology and beyond
- X. Chen
- S. Fang
- et al.
- 2006
- VLSI Technology 2006
Publications
Date
Featured collections
Popular topics
12 results for I.Y. Yang
Interaction of middle-of-line (MOL) temperature and mechanical stress on 90nm hi-speed device performance and reliability
- K.Y. Lim
- V. Chan
- et al.
- 2005
- ESSDERC 2005
65nm CMOS technology for low power applications
- A. Steegen
- R. Mo
- et al.
- 2005
- IEDM 2005
Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing
- H.S. Yang
- R. Malik
- et al.
- 2004
- IEDM 2004
Body voltage and history effect sensitivity to key device parameters in 90nm PD-SOI
- S. Kawanaka
- M.B. Ketchen
- et al.
- 2004
- IEEE International SOI Conference 2004
PD/SOI SRAM performance in presence of gate-to-body tunneling current
- Rajiv V. Joshi
- Ching-Te Chuang
- et al.
- 2003
- IEEE Transactions on VLSI Systems
Performance enhancement on sub-70 nm strained silicon SOI MOSFETS on ultra-thin thermally mixed strained silicon/SiGe on insulator(TM-SGOI) substrate with raised S/D
- B.H. Lee
- A.C. Mocuta
- et al.
- 2002
- IEDM 2002
Carbon implanted halo for super halo characteristic NFETs in bulk and SOI
- John Ellis-Monaghan
- Kam-Leung Lee
- et al.
- 2001
- ESSDERC 2001
Effects of gate-to-body tunneling current on PD/SOI CMOS SRAM
- R.V. Joshi
- C.T. Chuang
- et al.
- 2001
- VLSI Technology 2001
Controlling floating-body effects for 0.13μm and 0.10μm SOI CMOS
- S.K.H. Fung
- N. Zamdmer
- et al.
- 2000
- IEDM 2000