Vladimir Yanovski, Israel A. Wagner, et al.
Ann. Math. Artif. Intell.
We define and investigate the problem of electromigration faults caused by spot defects during VLSI manufacturing process. Analysis is given for a simple layout, and simulations are presented and discussed for a more complicated case. It is shown that in some cases, electromigration-dependent parametric faults can make a significant contribution to the total yield estimation. ©2004 IEEE.
Vladimir Yanovski, Israel A. Wagner, et al.
Ann. Math. Artif. Intell.
Arkadiy Morgenshtein, Alexander Fish, et al.
IEEE Transactions on VLSI Systems
Michael Moreinis, Arkadiy Morgenshtein, et al.
ICECS 2004
Oded Katz, Dan A. Ramon, et al.
IEEE Transactions on VLSI Systems