Enterprise Class On-Chip Accelerator Integration

The IBM Z® platform and the underlying processor chip designs supporting it are optimized for processing vast amounts of data and transactions, while delivering consistent system performance, throughput, and response latencies with a sustained processor utilization of over 90% under all workload conditions in a highly virtualized and secured computing environment. The IBM Telum® series of processor chip designs that support the platform introduced the industry to a novel modular scalable heterogeneous processor compute framework with an integrated multi-tier unified cache hierarchy all within one chip. The processor chip design leverages a unique approach to ensure all elements work in unison to continuously deliver performance to the evolving needs of mission critical workloads running on the platform while responding to those changing demands at processor clock speeds. This paper will detail the varying compute, accelerator, and cache units within the IBM Telum II processor chip design, how they adaptively work in unison with each other without generating a cacophony of agents competing for scarce hardware resources, and how this forms the backbone of the scalable multi-processor system that our modern economy is built upon.