Mayan Moudgill, Pradip Bose, et al.
IEEE International Performance, Computing and Communications Conference, Proceedings 1999
Paper
Environment for powerPC microarchitecture exploration
Abstract
A novel, high-speed, execution-driven (performance-only) simulator that achieves an order of magnitude speedup over prior PowerPC processor timers within IBM is described. Called Microarchitecture Exploration Toolset (MET), the model is amenable to validation against a pre-register-transfer-level (RTL) reference model by using systematically generated performance test cases. The MET's main tools include Turandot, Aria, and trace readers for various trace formats. By using exploration examples, it is shown that MET allows users to calibrate a model quickly, without losing its innate speed efficiency.
Related
Aporva Amarnath, Subhankar Pal, et al.
IEEE Computer Architecture Letters
Rajeev Balasubramonian, Jichuan Chang, et al.
IEEE Micro
Conference paper
Very low voltage (VLV) design
Ramon Bertran, Pradip Bose, et al.
ICCD 2017