A high-performance embedded DSP core with novel SIMD features
Jeff H. Derby, Jaime H. Moreno
ICASSP 2003
A novel, high-speed, execution-driven (performance-only) simulator that achieves an order of magnitude speedup over prior PowerPC processor timers within IBM is described. Called Microarchitecture Exploration Toolset (MET), the model is amenable to validation against a pre-register-transfer-level (RTL) reference model by using systematically generated performance test cases. The MET's main tools include Turandot, Aria, and trace readers for various trace formats. By using exploration examples, it is shown that MET allows users to calibrate a model quickly, without losing its innate speed efficiency.
Jeff H. Derby, Jaime H. Moreno
ICASSP 2003
Tianyu Jia, Paolo Mantovani, et al.
ESSCIRC 2022
Naorin Hossain, Alper Buyuktosunoglu, et al.
IEEE Computer Architecture Letters
Jaime H. Moreno, Victor Zyuban, et al.
IBM J. Res. Dev