Guénolé Lallement, Fady Abouzeid, et al.
IEEE JSSC
We present EPOCHS-1, a 12 nm, 64 mm2 system-on-chip (SoC) with a high degree of heterogeneity. It features four Linux-SMP-capable RISC-V cores, 14 different types of accelerators, a distributed memory hierarchy, and various peripherals. EPOCHS-1’s memory hierarchy has the flexibility to support a diverse set of accelerators and can scale to support complex applications with 34% and 25% reduction in latency and energy, respectively. A subset of the SoC’s 23 power and 35 clock domains is regulated with a fully-decentralized power-allocation scheme and hybrid unified voltage and frequency scaling (HUVFS) that combines an in-package switched regulator with a per-tile low dropout (LDO). Combined, these techniques achieve up to a 1.57× speedup versus a centralized power management baseline. Designed with an agile methodology, EPOCHS-1 is based on an open-source SoC architecture and features only open-source components, either third-party or newly designed, thus enabling design reuse for future research projects.
Guénolé Lallement, Fady Abouzeid, et al.
IEEE JSSC
Erik Loscalzo, Martin Cochet, et al.
VLSI Technology and Circuits 2024
Ankur Agrawal, Monodeep Kar, et al.
VLSI Technology 2023
Martin Cochet, Karthik Swaminathan, et al.
IEEE Micro