Gate movement for timing improvement on row based Dual-VDD designs

Abstract

The scale of technology node increases power-density dynamically. Various techniques are proposed to reduce the power consumption. One approach is Dual-Supply Voltage (DSV).DSV is to apply a lower supply voltage on selected non-critical gates for power saving while maintaining chip performance at the same time. In order to facilitate the power design in DSV, the same voltage gates are grouped to form islands. [21] presents a flow to generate and place voltage islands. However, after relocating gates to voltage islands, the original placement is changed and the timing might become worse. In this paper, we propose algorithms to redistribute gates for performance improvement. At the same time, all the DSV island/gate constraints are satisfied. On tested designs, our algorithm greatly improved the timing, and the final worst slack is less than 10ps worse than that of the original design.