Nicky Chau-Chun Lu, Tak H. Ning, et al.
IEEE Journal of Solid-State Circuits
A sensing scheme in which the bit line is precharged to half VDD is introduced for CMOS DRAM’s. The study shows that the half - VDDbit-line sensing scheme has several unique advantages, especially for highperformance high-density CMOS DRAM’s, when compared to the full- VDDbit-line sensing scheme used for NMOS memory arrays or the grounded bit-line sensing scheme for PMOS arrays in CMOS DRAM’s. © 1984, IEEE.
Nicky Chau-Chun Lu, Tak H. Ning, et al.
IEEE Journal of Solid-State Circuits
Hu H. Chao, Feng-Hsien W. Shih, et al.
IEEE Journal of Solid-State Circuits
Sang H. Dhong, Nicky Chau-Chun Lu, et al.
IEEE Journal of Solid-State Circuits
Nicky C. C. Lu, Hu H. Chao, et al.
IEEE Journal of Solid-State Circuits