HIERARCHICAL VLSI LAYOUT: SIMULTANEOUS PLACEMENT AND WIRING OF GATE ARRAYS.

Abstract

We present a new methodology for Design Automation of gate array VLSI layout. The traditional approach to VLSI layout design consists of two independent stages: placement of components and wire routing. This approach may not result in an appropriate layout, even if powerful placement and wiring techniques are applied. One of the main disadvantages of this traditional layout process, is that there are no known universal criteria for placement. The main objective of the in placement stage is to produce a placement for which the subsequent routing can be carried out successfully (a routable placement). We attempt to merge these two phases together in a hierarchical fashion, i. e. to provide a simultaneous solution of the placement and wiring stages of physical design.