High-speed low-power cross-coupled active-pull-down ECL circuit

This paper presents a high-speed low-power cross-coupled active-pull-down ECL (CC-APD-ECL) circuit. The circuit features a cross-coupled active-pull-down scheme to improve the power-delay of the emitter-follower stage. The cross-coupled biasing scheme preserves the emitter-dotting capability and requires no extra biasing circuit branch and power for the active-pull-down transistor. Based on a 0.8 μm double-poly self-aligned bipolar technology at a power consumption of 1.0 mW/gate, the circuit offers 1.7X improvement in the loaded (FI/FO = 3, CL = 0.3 pF) delay, 2.1X improvement in the load driving capability, and 3.5X improvement in the dotting delay penalty compared with the conventional ECL circuit. The design considerations of the circuit are discussed.