Hysteresis effect in pass-transistor based partially-depleted SOI CMOS circuits

Abstract

Pass-transistor based circuits such as Complimentary Pass-transistor Logic (CPL) have recently emerged as strong contenders for implementing high-performance arithmetic operations. The single-ended version known as LEAP offers the advantage of lower power in addition to high performance. The nMOS pass-transistor based circuits with partially-depleted SOI devices offer significant performance improvement over the bulk-CMOS due to the absence of reverse body effect in floating body configuration. In this regard, an experiment was conducted to examine the effects of hysteretic threshold voltage (Vt) on the performance of LEAP and CPL circuits.