Yao Qi, Raja Das, et al.
ISSTA 2009
The IBM POWER6™ microprocessor is a 790 million-transistor chip that runs at a clock frequency of greater than 4 GHz. The complexity and size of the POWER6 microprocessor, together with its high operating frequency, present a number of significant challenges. This paper describes the physical design and design methodology of the POWER6 processor. Emphasis is placed on aspects of the design methodology, technology, clock distribution, integration, chip analysis, power and performance, random logic macro (RLM), and design data management processes that enabled the design to be completed and the project goals to be met. © 2007 IBM.
Yao Qi, Raja Das, et al.
ISSTA 2009
John M. Boyer, Charles F. Wiecha
DocEng 2009
Reena Elangovan, Shubham Jain, et al.
ACM TODAES
Alfonso P. Cardenas, Larry F. Bowman, et al.
ACM Annual Conference 1975