Haoran Qiu, Weichao Mao, et al.
ASPLOS 2024
IBM Telum II is an 8 core 5.5 GHz microprocessor for the zNext system. Key capacity and performance improvements are achieved through enhancements to the core, AI accelerator, and the use of high-density SRAM cell to increase cache size. A new on-chip data processing unit is included with an initial use of IO acceleration. Telum II maintains high reliability and a power profile within 5% of the prior generation while simultaneously increasing frequency and increasing latch count by 40%.
Haoran Qiu, Weichao Mao, et al.
ASPLOS 2024
Jaewon Lee, Pier Andrea Francese, et al.
ISSCC 2025
Deming Chen, Alaa Youssef, et al.
arXiv
Jose Manuel Bernabe' Murcia, Eduardo Canovas Martinez, et al.
MobiSec 2024