Publications

2 results for Bill Huott

A 6+ GHz 128KB Multi-Port L1 Cache using Ground Rule Clean 10T Bitcells in 5nm Technology
- - Rajiv Joshi
  - John Davis
  - et al.
- 2025
- VLSI Technology and Circuits 2025
IBM Telum II Processor Design-Technology Co-Optimizations for Power, Performance, Area and Reliability
- - David Wolpert
  - Gerry Strevig
  - et al.
- 2025
- ISSCC 2025