IBM z14: Enabling physical design in 14-nm technology for high-performance, high-reliability microprocessors

Abstract

The IBM z14 design was built with the 14-nm high-performance silicon-on-insulator (SOI) technology of GLOBALFOUNDRIES. This was the first technology node after IBM transitioned from its integrated fabrication facility to operating in a fabless environment, driving significant changes to design processes and methodology. In addition to this partnership, the 14-nm technology introduced significant changes relative to previous technology nodes, including the introduction of fin-shaped field-effect transistors, the use of double patterning for the lowest back-end-of-line layers, and the introduction of middle-of-line layers to exploit contact layers for local interconnects. This combination of technical and business challenges required numerous large-scale innovations for our design, design team, and design methodologies. In this paper, we provide a survey of these innovations, including the fin-based standard cell image, deeply scaled SOI self-heating/electromigration verification, routing strategies to handle double-patterning with interlayer via awareness, fill automation to enable simultaneous design of multiple layers of hierarchy, and high-performance array design with the voltage and noise limitations of the 14-nm technology node.