Replacement metal gate resistance in FinFET architecture modelling, validation and extendibility
- Ruqiang Bao
- Brian Greene
- et al.
- 2015
- IEDM 2015
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19 results for Sungjae Lee
Off-state self-heating, micro-hot-spots, and stress-induced device considerations in scaled technologies
- Siyu Koswatta
- N. Mavilla
- et al.
- 2015
- IEDM 2015
A 0.039um2 high performance eDRAM cell based on 32nm high-K/metal SOI technology
- Nauman Z. Butt
- Kevin McStay
- et al.
- 2010
- IEDM 2010
Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond
- Ali Khakifirooz
- Kangguo Cheng
- et al.
- 2010
- ISSCC 2010
A 32 Gb/s, 4.7 pJ/bit Optical Link With-11.7 dBm Sensitivity in 14-nm FinFET CMOS
- Jonathan E. Proesel
- Zeynep Toprak-Deniz
- et al.
- 2018
- IEEE JSSC
Manufacturable parasitic-aware circuit-level FETs in 65-nm SOI CMOS technology
- Daeik Kim
- Jonghae Kim
- et al.
- 2007
- IEEE Electron Device Letters
A 32Gb/s, 4.7pJ/bit optical link with-11.7dBm sensitivity in 14nm FinFET CMOS
- Jonathan E. Proesel
- Zeynep Toprak-Deniz
- et al.
- 2017
- VLSI Circuits 2017
Symmetry breaking in the drain current of multi-finger transistors
- Ning Lu
- Sungjae Lee
- et al.
- 2015
- CICC 2015
Virtual de-embedding study for the accurate extraction of Fin FET gate resistance
- Shireen Warnock
- Rob Groves
- et al.
- 2014
- CICC 2014
Gate stack resistance and limits to CMOS logic performance
- Richard A. Wachnik
- S. Lee
- et al.
- 2013
- CICC 2013