In-Line Metrology for Sub-2nm Technology Nodes

In-line metrology is a key enabler for fast cycles of learning during development and for ensuring constant, optimum device performance during semiconductor manufacturing. Fast and non-destructive in-line techniques are required for dimensional and materials metrology – they are intended to capture process excursions in real-time (process monitoring) and can be used for advanced process control (feedback or feed-forward). Therefore, advanced metrology enables competitive and economical development as well as high-volume manufacturing.
As the industry keeps scaling to fulfill Moore’s law, new architectures such as the nanosheet gate-all-around transistor have emerged and already transitioned into manufacturing at the 3 nm node. The 3D nature of this device architecture with its stacked channels came with demanding process specifications and mandated a significant metrology leap. The many new process steps, mostly related to the channel formation, require tight control and sheet-specific metrology to achieve and maintain desired device performance. Furthermore, the introduction of EUV lithography enabled further scaling and opened a large design space, which in turn requires additional metrology and novel concepts for future exposure tool mix and matching, for example. Figure 1 depicts a simplified view on where the industry is headed: a backside power delivery network (BSPDN) has been demonstrated already for finFET technology and is expected to be added next generation nanosheet devices. This requires wafer bonding to a carrier wafer, subsequent wafer thinning, and backside processing to electrically contact the devices. Monitoring the bonding process is critical as wafer warpage can have significant implications for backside overlay. The wafer thinning process must be precisely controlled and metrology from the backside will not be straightforward as the original frontside comprises full wafer device patterning. The next device evolution is projected to be stacking FETs on top of each other before the traditional Si or SiGe channels will be replaced by new 2D transition metal dichalcogenide semiconductors such as MoS2 or WSe2. In any case, the stacked FET architecture will add significant complexity beyond nanosheet technology, especially to model-based techniques such as optical scatterometry. The introduction of 2D materials into semiconductor manufacturing will likely require another wave of lab-to-fab transitions related to metrology techniques. While one of the key techniques, Raman spectroscopy, has made its introduction into the fab just recently, others are required for comprehensive process and materials characterization. In addition to traditional transistor scaling, efforts are underway to monolithically integrate functional elements such as embedded magnetoresistive random-access memory (MRAM) or phase-change memory (PCM) for analog AI applications. These devices introduce new materials into the back-end-of-line (BEOL) processing and require dedicated and demanding metrology efforts.
Besides traditional, monolithic integration, the industry is also moving towards heterogeneous integration and chiplet technology, which means that individual components (dies or chiplets) may be stacked on top of each other and/or are jointly placed on an interposer. The advanced packaging evolution has entirely different metrology requirements compared to the logic scaling ones discussed above. Through-silicon via (TSV) characterization from the front and backside, pre and post metrology for defect-free hybrid wafer bonding, large feature wafer level measurements, and die to die overlay all come along with a new set of challenges. Metrology developments are required for every process step, and techniques that have been introduced to semiconductor manufacturing only recently are expected to gain more importance as the industry continues the path to ever more powerful computational devices.