Modeling polarization for Hyper-NA lithography tools and masks
Kafai Lai, Alan E. Rosenbluth, et al.
SPIE Advanced Lithography 2007
Reduced power dissipation relative to the field-effect transistor (FET) is a key attribute that should be possessed by any device that has a chance of supplanting the FET as the ubiquitous building block for complex digital logic. We outline the possible physical approaches to achieving this attribute, and illustrate these approaches by citing current exploratory device research. We assess the value of the key exploratory research objectives of the semiconductor industry-sponsored Nanoelectronics Research Initiative (NRI) in the light of this pressing need to reduce dissipation in future digital logic devices. © 2006 IEEE.
Kafai Lai, Alan E. Rosenbluth, et al.
SPIE Advanced Lithography 2007
Robert C. Durbeck
IEEE TACON
Fan Zhang, Junwei Cao, et al.
IEEE TETC
Elena Cabrio, Philipp Cimiano, et al.
CLEF 2013