Christos Vezyrtzis, T. Strach, et al.
ISSCC 2018
A highly efficient loop-based interconnect modeling methodology is proposed for multigigahertz clock network design and optimization. Closed-form loop resistance and inductance models are proposed for fully shielded global clock interconnect structures, which capture high-frequency effects including inductance and proximity effects. The models are validated through comparisons with electromagnetic simulations and measured data taken from a Power4 chip. This modeling methodology greatly improves the clock interconnect simulation efficiency and enables fast physical design exploration. Examples of interconnect performance optimization are demonstrated and design guidelines are proposed.
Christos Vezyrtzis, T. Strach, et al.
ISSCC 2018
Nancy Y. Zhou, Phillip Restle, et al.
SLIP 2014
Xuejue Huang, Phillip Restle, et al.
Proceedings of the Custom Integrated Circuits Conference
David Shan, Phillip Restle, et al.
VLSI Circuits 2015