Conference paper
AGAR: A single-layer router for gate array cell generation
Mark A. Mostow
ICCAD 1989
A method is presented for floorplanning data-path chips by a technique of multiterrain partitioning with integrated global wiring to partition the objects into terrains, followed by multistack placement and standard-cell placement. Requirements on terrain size, terrain shape, wirability, and timing are considered. Results obtained for some chip designs are presented.
Mark A. Mostow
ICCAD 1989
W.K. Luk, Alvar A. Dean
DAC 1989
W.K. Luk, Paolo Sipala, et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
W.K. Luk, D.T. Tang, et al.
DAC 1986