A compact low-power 3D I/O in 45nm CMOS
- Yong Liu
- Wing Luk
- et al.
- 2012
- ISSCC 2012
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16 results for Wing Luk
A fast physical constraint generator for timing driven layout
- W.K. Luk
- 1991
- DAC 1991
Multi-stack optimization for data-path chip (microprocessor) layout
- W.K. Luk
- Alvar A. Dean
- 1989
- DAC 1989
Hierarchical global wiring for custom chip design
- W.K. Luk
- D.T. Tang
- et al.
- 1986
- DAC 1986
Minimum-Area Wiring for Slicing Structures
- W.K. Luk
- Paolo Sipala
- 1987
- IEEE TC
POWER8 design methodology innovations for improving productivity and reducing power
- Matthew M. Ziegler
- Ruchir Puri
- et al.
- 2014
- CICC 2014
A multi-bit error detection scheme for DRAM using partial sums with parallel counters
- Balaji Narasimham
- Wing K. Luk
- 2008
- IRPS 2008
A 3-transistor DRAM cell with gated diode for enhanced speed and retention time
- Wing K. Luk
- Jin Cai
- et al.
- 2006
- VLSI Circuits 2006
2T1D memory cell with voltage gain
- Wing K. Luk
- Robert H. Dennard
- 2004
- VLSI Circuits 2004
Development of a high bandwidth merged logic/DRAM multimedia chip
- W.K. Luk
- Y. Katayama
- et al.
- 1997
- ICCD 1997