M.S. Murthy, Mohit Bajaj, et al.
PVSC 2013
In this paper, we present a fully-coupled and self-consistent continuum based three-dimensional numerical analysis to understand hot carrier and device self-heating effects for device-circuit co-optimization in Si gate-all-around nanowire FETs. We employ three-moment based energy transport formulations and two-dimensional quantum confinement effects to demonstrate negative differential conductivity in Si nanowire FETs and assess its impact on a CMOS inverter and three-stage ring oscillator. We show that strong two-dimensional quantum confinement yields volume inversion conditions in Si nanowire FETs and surround gate geometry enables better short-channel effect control. We find that hot carrier and self-heating effects can degrade ON-state current in Si nanowire FETs and severely limit the logic circuit performance due to the introduction of higher signal propagation delays. © 2014 The Japan Society of Applied Physics.
M.S. Murthy, Mohit Bajaj, et al.
PVSC 2013
Phil Oldiges, R. Muralidhar, et al.
SISPAD 2011
Ankur Arya, Balaji Jayaraman, et al.
IWPSD 2011
Aniruddha Konar, John Mathew, et al.
Nano Letters