Chunjian Ni, Rajiv V. Joshi, et al.
ASME Electronic and Photonics Packaging Division 2007
This brief paper presents a high-speed low-power non-threshold-logic (NTL) based push-pull logic circuit featuring a complementary emitter-follower driver. Compared with the standard NTL circuit, the circuit offers a much better balance between the pull-up and pull-down delay, improved scalability, and superior load driving capability. Simulation results based on a 0.8-μm double-poly self-aligned complementary bipolar technology indicate that at a power consumption of 1.22 mW/gate, the circuit offers 2.4× improvement in the pull-down delay of a loaded gate and 4.0× improvement in the load driving capability over the standard NTL circuit. The design and scaling considerations of the circuit are discussed. © 1991 IEEE
Chunjian Ni, Rajiv V. Joshi, et al.
ASME Electronic and Photonics Packaging Division 2007
Keunwoo Kim, Koushik K. Das, et al.
VLSI-DAT 2007
Rajiv Joshi, Rouwaida Kanj, et al.
ISLPED 2007
Meng-Hsueh Chiang, Jeng-Nan Lin, et al.
IEEE Transactions on Electron Devices