Reinaldo A. Bergamaschi, Salil Raje, et al.
IEEE Transactions on VLSI Systems
Verifying equivalence of the behavioral specification and scheduled implementation is a significant problem in high-level synthesis, because scheduling changes the cycle-by-cycle behavior. The authors present a practical method for comparing simulation results for the two using the same vectors.
Reinaldo A. Bergamaschi, Salil Raje, et al.
IEEE Transactions on VLSI Systems
Reinaldo A. Bergamaschi, Raul Camposano, et al.
Integration, the VLSI Journal
Reinaldo A. Bergamaschi
SLIP 2004
Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, et al.
IEEE Design and Test of Computers