Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, et al.
IEEE Design and Test of Computers
Verifying equivalence of the behavioral specification and scheduled implementation is a significant problem in high-level synthesis, because scheduling changes the cycle-by-cycle behavior. The authors present a practical method for comparing simulation results for the two using the same vectors.
Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, et al.
IEEE Design and Test of Computers
Daniel Brand, Reinaldo A. Bergamaschi, et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Nagu Dhanwada, Reinaldo A. Bergamaschi, et al.
Des Autom Embedded Syst
Hiren D. Pate, Sandeep K. Shukla, et al.
DATE 2006