Conference paper
SEAS: A System for Early Analysis of SoCs
Reinaldo A. Bergamaschi, Youngsoo Shin, et al.
CODES+ISSS 2003
Paper
Observable time windows: Verifying high-level synthesis results
Abstract
Verifying equivalence of the behavioral specification and scheduled implementation is a significant problem in high-level synthesis, because scheduling changes the cycle-by-cycle behavior. The authors present a practical method for comparing simulation results for the two using the same vectors.
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Integration, the VLSI Journal