Meng-Hsueh Chiang, Keunwoo Kim, et al.
IEEE International SOI Conference 2004
Optimal design for nanowire FETs beyond 22 nm technology node is presented using numerical 3D simulation and physical analysis. Our results suggest that design optimization associated with the wire diameter could achieve performance benefits in the nanowire FET technologies. Small wire diameter is not necessary for performance, though it favors device scaling. © 2009 IEEE.
Meng-Hsueh Chiang, Keunwoo Kim, et al.
IEEE International SOI Conference 2004
Yi-Bo Liao, Meng-Hsueh Chiang, et al.
Microelectronics Journal
Ashish Goel, Sumeet Gupta, et al.
DRC 2009
Yi-Bo Liao, Meng-Hsueh Chiang, et al.
NSTI-Nanotech 2011