Optimization of Scannable Latches for Low Energy

Abstract

This paper covers a range of issues in the design of latches and flip-flops for low-power applications. First it revisits, extends, and improves the energy-performance optimization methodology, attempting to make it more formal and comprehensive. The data-switching factor and the glitching activity are taken into consideration, using a formal analytical approach, then a notion of an energy-efficient family of configurations is introduced to make the comparison of different latch styles in the energy-performance space more fair. A recently proposed methodology for balancing hardware intensity in processor pipelines is applied to latch design to facilitate the selection of the objective function for tuning transistor sizes. The power dissipation of the clock distribution is taken into account, supported by simulations of extracted netlists for multibit datapath registers. Practical issues of building a low overhead scan mechanism are considered, and the power overhead of the scannable design is analyzed. A low-power level-sensitive scan mechanism is proposed, and results of a comparative study of scannable latches are shown. The applicability of the proposed scan mechanism to a wide variety of latches is demonstrated.