S.M. Sadjadi, S. Chen, et al.
TAPIA 2009
The IBM System z10™ Enterprise Class mainframe addresses the modern data center requirements for minimizing floor space while increasing computing power efficiency. These objectives placed challenges on the z10™ packaging design as a result of significantly increased demand on system packaging density, power delivery, and logic and power cooling efficiency compared with the recent IBM System z9® and z990 mainframe generations. Several innovations were implemented to successfully meet these challenges: a more powerful multichip module (MCM) that delivers denser computing capability and a 64-way system; a vertically mated processor unit (PU) book structure that achieves a more efficient thermal implementation and a higher signal bandwidth between processors; and a PU book-centric dc-dc power delivery design that is more efficient. This paper presents the key elements to achieve this design: the novel mechanical load transmission paths and the connector technologies for the MCM, PU book, I/O, and power regulation components; an innovative cooling and thermal design that includes component-level tolerance of failures; and improved power delivery and power code developments to maximize the overall z10 compute efficiency. © Copyright 2009 by International Business Machines Corporation.
S.M. Sadjadi, S. Chen, et al.
TAPIA 2009
Chi-Leung Wong, Zehra Sura, et al.
I-SPAN 2002
Michael D. Moffitt
ICCAD 2009
Sabine Deligne, Ellen Eide, et al.
INTERSPEECH - Eurospeech 2001