High-speed low-power cross-coupled active-pull-down ECL circuit
C.T. Chuang, B.S. Wu, et al.
BCTM 1993
'Tapered gate' is a device sizing methodology to improve the performance of critical paths in stacked circuit configurations. This paper presents a detailed study of the performance leverage of tapered gate in a partially depleted silicon-on-insulator (PD/SOI) technology. It is shown that the reduced junction capacitance in a PD/SOI device renders the series resistance reduction of the lower transistors in the stack more effective. The effects are also shown to be more pronounced for low-VT cases. The study demonstrates that tapered gate remains a viable device sizing technique/methodology for improving performance in a PD/SOI technology.
C.T. Chuang, B.S. Wu, et al.
BCTM 1993
C.T. Chuang
VLSI Circuits 1990
R.V. Joshi, José A. Pascual-Gutiérrez, et al.
ESSDERC 2005
R.V. Joshi, W. Hwang, et al.
ISLPED 2000