SOI for a 1-Volt CMOS Technology and Application to a 512kb SRAM with 3.5 ns Access Time
- G. Shahidi
- T.H. Ning
- et al.
- 1993
- IEDM 1993
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19 results for Michael Rosenfield
High Performance 0.1 μm CMOS Devices with 1.5 V Power Supply
- Y. Taur
- S.J. Wind
- et al.
- 1993
- IEDM 1993
The smart grid and key research technical challenges
- Michael G. Rosenfield
- 2010
- VLSI Technology 2010
Variability and power management in sub-100nm SOI technology for reliable high performance systems
- Koushik Das
- Kerry Bernstein
- et al.
- 2008
- IEEE International SOI Conference 2008
Performance analysis of tapered gate in PD/SOI CMOS technology
- W. Hwang
- C.T. Chuang
- et al.
- 2001
- VLSI-TSA 2001
Mixed e-beam/optical lithography process for the fabrication of sub-0.25-μm poly gates
- Keith T. Kwietniak
- Michael G. Rosenfield
- et al.
- 1993
- Microlithography 1993
Overlay measurements using the scanning electron microscope: accuracy and precision
- Michael G. Rosenfield
- 1992
- Microlithography 1992
The use of the low voltage SEM in IC fabrication
- Michael G. Rosenfield
- 1991
- Scanning
Contrast and sensitivity trade-offs of resist processing in electron beam lithography at 0.5µm and below
- W. Molzen
- Michael G. Rosenfield
- et al.
- 1989
- Proceedings of SPIE 1989
The COVID-19 High-Performance Computing Consortium
- Jim Brase
- Nancy Campbell
- et al.
- 2021
- Computing in Science and Engineering