Performance modeling and characterization of large last level caches

Abstract

Different workloads exhibit different memory footprint and have different dependency on the size and configuration of the memory hierarchy. To quantify the performance implication of various memory system architectures and attributes one needs to understand the program behavior of an application/workload and its use of the memory subsystem. One such architecture studied in this paper is where multiple memory technologies are integrated into the memory system with one (typically the faster, more expensive technology) acting as a large cache for the other (typically a slower, cheaper technology). We develop a large cache prototype to study the performance of different applications and their sensitivity to different architecture parameters. The prototype measures different metrics associated with a cache performance which are in turn used to characterize the performance implications of such a memory architecture on different workloads and the dependency on different configuration parameters. © 2012 IEEE.