Performance modeling and characterization of large last level caches
- Parijat Dube
- Michael Tsao
- et al.
- 2012
- MASCOTS 2012
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9 results for Michael Tsao
Performance modeling and characterization of large last level caches
- Parijat Dube
- Michael Tsao
- et al.
- 2012
- ISPASS 2012
Architectural design for next generation heterogeneous memory systems
- Alan Bivens
- Parijat Dube
- et al.
- 2010
- IMW 2010
Program behavior characterization in large memory systems
- Parijat Dube
- Michael Tsao
- et al.
- 2010
- ISPASS 2010
SP1 high-performance switch
- Craig B. Stunkel
- D.G. Shea
- et al.
- 1994
- SHPCC 1994
Architecture and implementation of Vulcan
- Craig B. Stunkel
- D.G. Shea
- et al.
- 1994
- IPPS 1994
Blue Gene/L torus interconnection network
- Narasimha R. Adiga
- Matthias A. Blumrich
- et al.
- 2005
- IBM J. Res. Dev
Verification strategy for the Blue Gene/L chip
- Michael E. Wazlowski
- Narasimha R. Adiga
- et al.
- 2005
- IBM J. Res. Dev
SP2 high-performance switch
- Craig B. Stunkel
- D.G. Shea
- et al.
- 1995
- IBM Systems Journal