A high-resolution side-channel attack on last-level cache
Mehmet Kayaalp, Nael Abu-Ghazaleh, et al.
DAC 2016
This paper considers the practical nuances of using current source gate models in an industrial statistical timing analysis environment. Specifically, the memory overhead of a naive implementation combining statistical and current source models to obtain and store gate output waveforms is found to be impractical for large microprocessor designs. A study is performed to observe variational gate output waveforms, and a technique is presented to store the waveforms in a memory efficient manner with minimal accuracy impact. The presented technique is validated over a set of 14 nanometer designs, and has enabled the usage of current source models in our industrial statistical timing analysis flow. Results demonstrate slack accuracy improvements of up to 17 picoseconds with a 1.15X run-time overhead and 1.1 gigabytes per million-gates memory overhead in comparison to an existing flow.
Mehmet Kayaalp, Nael Abu-Ghazaleh, et al.
DAC 2016
Chandu Visweswariah, Vladimir Zolotov, et al.
VTS 2009
Jinjun Xiong, Vladimir Zolotov, et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Jinjun Xiong, Vladimir Zolotov, et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems