Relief printing of micron-sized electrical conductive structures on silicon

Abstract

Copper is the metal of choice for electrical circuits in electronics. It is lower in cost than silver and offers excellent electrical properties like low electrical resistivity and electromigration resistance. Physical vapor deposition and wet-chemical etching or electroforming are the standard processes used to deposit and pattern copper on silicon and in printed-circuit-board technology. Recently, copper inks and pastes have become available for the printing of copper films, with the potential outcome of lowering the production cost beyond that of the established processes. Furthermore, the printing processes are compatible with role-to-role fabrication, and are hence attractive for flexible electronics. In this study, a bi-modal copper paste containing nano-and micro-particles is transferred in a relief printing process by using silicon stamps. It was possible to demonstrate electrical conductive tracks with a linewidth down to 8 μm. The spacing between neighboring tracks is related to their width and can be as low as 10 μm. It was possible to achieve a sheet resistance of less than 8mOsq-1 after formicacid-assisted sintering at 180 °C. The low sintering temperature enables the direct placement of electronic components without additional soldering and thus saves time and production costs.