Restructuring VLSI layout representations for efficiency

Abstract

VLSI mask layouts usually have a hierarchical representation which serves to record the structure of the design while saving storage space. It is often convenient to work directly on such a representation for performing some operations. However for many other operations it is preferable to work on the flattened representation of the circuit. In this paper we look at the unnesting operation on layouts to demonstrate that simple transformations of one hierarchy to an equivalent one help tremendously in improving the performance of typical operations on hierarchical layout representations, while not requiring as much memory as flattened representations.